One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the perimeter of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side, resulting in crowding of the solder bumps along the perimeter of the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart about 0.1 millimeter or less.
Wirebonding is the most common technique for establishing electrical connection between the bonding pads on the surface of a chip or die and the inner lead terminals, or posts, on the leadframe or substrate. A section of a typical conventional wirebonded chip 26 is shown schemalically in FIG. 1 and may include multiple wire bonding balls 10, each of which is directly bonded to the continuous upper surface of a bonding pad 14, typically rectangular in configuration, as shown in FIG. 2, and partially covered by a passivation layer 12. A pad opening 13 in the passivation layer 12 exposes the bonding pad 14, through which pad opening 13 the bonding ball 10 extends. The bondinq pad 14 is surrounded by a dielectric layer 15 such as an oxide in the chip 26. As further shown in FIG 1, the bonding pad 14 is provided in electrical contact with an upper conductive layer 16, which is separated from an underlying conductive layer 22 by an insulatlve layer 18. The conductive layers 16, 22 are disposed in electrical contact with each other through conductive vias 20 that extend through the insulative layers 18. The various insulative layers 18 and conductive layers 22 are sequentially deposited on a silicon substrate 24 throughout semiconductor fabrication, in conventional fashion. Each bonding ball 10 connects a bonding wire 11 through a lead to the terminals (not shown) on a leadframe.
The bonding pads 14 are typically arranged in rows which extend adjacent to respective edges of the chip 26. Prior to packaging and formation of the bonding balls 10 on the respective bonding pads 14, the chip 26 is subjected to parametric testing which utilizes test structures to assess the electrical characteristics and reliability of the devices on the wafer. Probe cards are typically used as an interface between the devices on the chip and automated test equipment. The probe card typically includes a printed circuit board from which extends multiple probe needles (not shown), each of which is disposed in electrical contact with the device through the respective bonding pads 14. Each probe needle typically contacts the approximate center of the bonding pad 14 at a pressure of typically about 2–3 grams. Consequently, the probe needle typically forms a scrub mark (not shown) in the center of the bonding pad 14.
After the chip 26 is subjected to parametric testing, the wire bonding balls 10 are formed on the respective bonding pads 14 and a bonding wire 11 is bonded to each bonding ball 10, as shown in FIG. 1. Alternatively, each bonding wire 11 may be bonded directly to the surface of each bonding pad 14. The chip 26 may then be subjected to physical pressure tests in which shear and other forces are applied to the bonding wire 11 and bonding pad 14. One of the problems which typically occurs during such testing is that each bonding pad 14 tends to exert pressure against the adjacent dielectric layer 15, frequently forming a crack 17 or otherwise damaging the dielectric layer 15 in the region surrounding the bonding pad 14, as shown in FIG. 3. Moreover, upon application of a lifting force to the bonding wire 11, the bonding pad 14 may be pulled out of the dielectric layer 15. With the interconnect dimensions of VLSI devices scaling down to submicron levels, dielectric layers are increasingly being formed using low-k dielectric materials, which are characterized by weaker mechanical and physical properties than materials having a higher dielectric constant. Accordingly, various methods have been used to reinforce the bonding pads 14 in the dielectric layer 15 to prevent or minimize damage to the dielectric layer 15 and prevent the bonding pads 14 from being inadvertently pulled out of the dielectric layer 15 during physical testing of the chip 26.
FIG. 4 illustrates a conventional wirebonded chip 32 in which a bonding wire 30 has been bonded to a bonding pad 31 in a dielectric layer 34 using a thermosonic ball bond 28. Multiple conductive layers 36 are separated from each other by insulative layers 38, and the conductive layers 36 are connected to each other and to the bonding pad 31 through vias 40 which extend through the insulative layers 38. As shown in FIG. 4, one conventional method of reducing or eliminating damage to the dielectric layer 34 and lift-off of the bonding pad 31 during physical testing of the chip 32 includes providing a metal anchor pad 42 in the dielectric layer 34, in spaced-apart relationship to each bonding pad 31, and connecting the anchor pad 42 to the bonding pad 31 through a metal bridge 44. Accordingly, a portion of the stress which is applied to the dielectric layer 34 and to the bonding pad 31 is absorbed by the anchor pad 42 and the anchor bridge 44. Another method involves attaching the thermosonic ball bond 28 of the bonding wire 30 to the anchor pad 32 rather than to the bonding pad 31. While these methods are somewhat effective in preventing damage to the chip 32 during testing thereof, the dielectric layer 34, particularly if it has a low dielectric constant, still has a tendency to crack frequently during such testing. Accordingly, a new and improved structure and method is needed for preventing damage to a wire-bonded chip during physical testing of the chip.
An object of the present invention to provide a new and improved structure and method for reinforcing or anchoring a bonding pad in a dielectric layer.
Another object of the present invention is to provide a new and improved structure and method which prevents cracking of a dielectric layer during testing of a chip.
Still another object of the present invention is to provide a structure and method which is applicable to wire-bonded chips.
Another object of the present invention is to provide a new and improved, parallel interconnect structure for stabilizing or anchoring a bonding pad in a dielectric layer on a chip.
Yet another object of the present invention is to provide a structure and method which enhances the structural and functional integrity of a chip.
A still further object of the present invention is to provide a new and improved method which prevents bonding pads from being inadvertently pulled from a dielectric layer during testing of wire-bonded chips.
Yet another object of the present invention is to provide a new and improved bonding pad structure which includes a bonding pad provided in a dielectric layer, at least one conductive layer provided in electrical contact with the bonding pad, and an anchor structure contacting the bonding pad and the conductive layer for anchoring and reinforcing the bonding pad in the dielectric layer.
A still further object of the present invention is to provide a new and improved structure and method which is applicable to flip-chip packaging technology.